module ysyx_22040213_WBReg(
	input clk,
	input rst,
	
	input MEM_to_WB_valid,
	input WB_ready_go,
	input REG_allow_in,
	
	output WB_allow_in,
	output WB_to_REG_valid,

	input [4:0] i_wb_rd,
	input i_wb_w_en,
	input [63:0] i_wb_wdata,
	output [4:0] o_wb_rd,
	output o_wb_w_en,
	output [63:0] o_wb_wdata,
//for difftest//
	input [31:0] i_wb_inst,
	input [63:0] i_wb_dnpc,
	input i_wb_id_bubble,
	input i_wb_exe_bubble,
	input i_wb_devices_access,

	output [31:0] o_wb_inst,
	output [63:0] o_wb_dnpc,
	output o_wb_id_bubble,
	output o_wb_exe_bubble,
	output o_wb_devices_access


);
	reg WB_valid;

	assign WB_allow_in = !WB_valid || WB_ready_go && REG_allow_in; //	EXEReg_allow_in;
	assign WB_to_REG_valid = WB_valid && WB_ready_go;

	always @(posedge clk)begin
	  if(rst)begin
	    WB_valid <= 1'b0;
	  end
	  else if(WB_allow_in)begin
	    WB_valid <= MEM_to_WB_valid;
	  end
	end

	wire w_en;
	assign w_en = MEM_to_WB_valid && WB_allow_in;

	reg o_wb_w_en_i;
	assign o_wb_w_en = WB_valid && o_wb_w_en_i;


	Reg #(5,  5 'b0) i0 (clk, rst, i_wb_rd, o_wb_rd, w_en);
	Reg #(1,  1 'b0) i1 (clk, rst, i_wb_w_en, o_wb_w_en_i, w_en);
	Reg #(64, 64'b0) i2 (clk, rst, i_wb_wdata, o_wb_wdata, w_en);
//for difftest//
	Reg #(32, 32'b0)  i3 (clk, rst, i_wb_inst, o_wb_inst, w_en);
	Reg #(64, 64'b0)  i4 (clk, rst, i_wb_dnpc, o_wb_dnpc, w_en);
	Reg #(1,   1'b0)  i5 (clk, rst, i_wb_id_bubble, o_wb_id_bubble, w_en);
	Reg #(1,   1'b0)  i6 (clk, rst, i_wb_exe_bubble, o_wb_exe_bubble, w_en);
	Reg #(1,   1'b0)  i7 (clk, rst, i_wb_devices_access, o_wb_devices_access, w_en);

endmodule
